Advanced Packaging Development Engineer

Summary

Apple’s Advanced Packaging team is seeking an experienced Packaging Development Engineer to drive next-generation packaging integration and technology development for future products. In this role, you will lead the definition, development, and qualification of cutting-edge 2.5D and 3D packaging technologies—incorporating features such as hybrid bonding, high-density interposers, fine-pitch microbumps, and Through-Silicon Vias (TSVs).

You will work cross-functionally with silicon design, physical design, SI/PI, thermal, and manufacturing teams to guide technologies from early architecture exploration through qualification and high-volume manufacturing.

Description

In this role, you will be responsible for advanced package integration and technology development within a cross-functional team, driving novel 2.5D/3D architectures from early concept through qualification.

Responsibilities

• Develop Advanced Packaging Architectures: Lead the definition, development, and qualification of advanced packaging technologies featuring hybrid bonding, fine-pitch microbumps, interposers, and TSVs.
• Define & Execute Test Vehicles: Design experimental test vehicles, establish packaging design rules, and lead characterization to validate novel interconnect concepts and build confidence for product integration.
• Manage Chip-Package Interaction & Reliability: Assess CPI risks, correlate mechanical and thermal stress behaviors, and partner with failure analysis teams to resolve yield, material, and structural challenges.
• Drive Cross-Functional Co-Optimization: Collaborate across architecture, silicon design, SI/PI, and thermal teams to evaluate holistic system trade-offs across performance, power, reliability, and cost.
• Lead External Technology Partners: Direct foundry and OSAT partners on technology roadmaps, process capability targets, development schedules, and high-volume manufacturing ramp.

Minimum Qualifications

• Bachelor’s degree required

Preferred Qualifications

• Strong technical background in 2.5D/3D packaging and semiconductor integration schemes (such as hybrid bonding, interposers, fine-pitch microbumps, and TSVs).
• Solid grasp of fab BEoL/MEoL interconnect processing, wafer-level packaging, and advanced assembly flows.
• Understanding of packaging materials, thermo-mechanical reliability, and chip-package interaction failure mechanisms.
• Broad systems mindset with the ability to balance package-level choices against silicon, electrical, thermal, and manufacturing constraints.
• Experience utilizing layout, physical design, or modeling tools alongside engineering data analysis.
• Proven track record collaborating with and driving external foundries, OSATs, or material vendors.
• Excellent communication and collaboration skills across cross-functional hardware teams.
• Education & Experience
• Degree: B.S., M.S., or Ph.D. in Physics, Materials Science, Electrical Engineering, Mechanical Engineering, Computer Engineering, or a related technical discipline.