FY27 Intern- AI-Driven Power Modeling for Evaluating Power Consumption in NoC IP Architectures - Guyancourt, 6 months

Company:

Qualcomm France S.A.R.L.

Job Area:

Interns Group, Interns Group > Interim Intern

General Summary:

ABSTRACT 

This internship investigates the impact of power consumption of Network-on-Chip (NoC) architectures and develops an AI/ML-based power modeling framework to estimate power consumption during early design stages. The objective is to enable fast and accurate evaluation of design choices while accounting for the effects of NoC IP Architectures, thereby facilitating power-aware architectural optimization. 

CONTEXT 

QITC develops and deploys highly configurable custom-built NoC IPs, tools and methodologies so that worldwide SoC teams can assemble SoCs with the desired Power-Performance-Area (PPA) characteristics. The NoC IP Architectures/Topologies directly shape the power profile of the interconnect, yet their impact can today only be quantified late in the flow, through synthesis, gate-level simulation and power analysis. Repeating this flow for every architectural option is prohibitively slow, which limits early power-aware exploration.

MISSION & METHOD 

The intern will build a two-phase framework combining classical power characterization with machine-learning-based power modeling:

Phase1: Data Preparation

1. Design & scenario setup — Elaborate NoC IP Architectures/Topologies and define representative traffic.

2. Power characterization — Run synthesis and simulations to capture activities profile and power.

3. Dataset construction — Build a labelled dataset from the power characterization step (2)

Phase2: ML based Modeling and Power Estimations

1. AI power modeling — Train and compare AI Based models and assess accuracy against gate-level references.

2. Early design-space exploration — Use the trained models to explore design in terms of power in seconds rather than hours.

EXPECTED DELIVERABLES 

• An automated power characterization for NoC IPs

• A reusable power dataset and AI power models, with documented accuracy and speed-up assessment.

• A prototype exploration tool and guidelines for power-aware NoC architecture choices.

PROFILE & PRACTICAL INFORMATION 

• Final year master’s degree in Microelectronics, Computer Engineering or a related field; interest in digital design, low power and machine learning.

• Scripting in Python and bash; notions of Verilog/VHDL, UVM, EDA flows and ML frameworks are a plus. Proficient in English.

• Duration: 6 months

*References to a particular number of years experience are for indicative purposes only. Applications from candidates with equivalent experience will be considered, provided that the candidate can demonstrate an ability to fulfill the principal duties of the role and possesses the required competencies.

Qualcomm expects its employees to abide by all applicable policies and procedures, including but not limited to security and other requirements regarding protection of Company confidential information and other confidential and/or proprietary information, to the extent those requirements are permissible under applicable law.

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