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CPU Physical Design (RTL Feasibility)

NUVACORE

Austin, TX · Bangalore View all 3 locations
  • Austin, TX
  • Bangalore
  • Santa Clara, CA
  • $140,000–$250,000 per year
  • Hybrid
  • Full Time
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About the role

At NUVACORE we're designing a new general-purpose CPU core for the sustained, intensive demands of AI infrastructure and agentic computing, not the workloads of the past. As physical design engineers focused on design feasibility you will focus on providing power, performance, and area feedback to the RTL team to ensure the design achieves all metrics and targets.  

THE ROLE

As a CPU Physical Design (PD) Engineer, you will participate in the following : 

  • Lead RTL/micro-architecture feasibility studies, providing actionable feedback to design teams.

  • Drive PPA outcomes for CPU units with a focus on timing closure and power optimization.

  • Collaborate cross-functionally with CPU unit owners, custom circuit designers, CAD, RTL/micro-architecture, and performance modeling teams.

  • Own the RTL intake process for the PD team, enforcing quality standards and ensuring design readiness before RTL handoff.

MINIMUM QUALIFICATIONS

  • Hold a BS or MS degree with 12+ years of experience (for Lead roles) or 5+ years of experience (for Individual Contributor roles) in CPU physical design.

  • Strong foundation in CPU micro-architecture (µArch) concepts and design principles.

  • Experience in CPU RTL feasibility, including RTL synthesis and floor planning. 

  • Deep expertise in timing analysis and timing ECO. 

  • Proficiency with Synopsys or Cadence EDA tools for PD in CPU design context. 

  • Demonstrated history of successful production tape-outs. 

  • Track record of driving PPA optimization for CPU units through effective RTL feedback and cross-functional collaboration. 

  • Comprehensive understanding of end-to-end physical design closure across all sign off domains.

  • Strong communication skills with the ability to build processes and infrastructure from the ground up

REQUIREMENTS — PREFERRED

  • Experience with some CPU units as block ownership taking from RTL to GDS (Tape-out).

  • Proven track record in PPA optimization across CPU designs and EDA tooling

  • Deep expertise in Physical Design (PD) sign off methodologies, including Formal Equivalence Verification (FEV), Voltage & Clock LP (VCLP), EM/IR analysis, Static Timing Analysis (STA), Extraction (EXT), and associated sign-off flows

  • Proficiency in Python, Perl, and TCL for design automation and flow development.

  • Experience in using Agentic AI tools for productivity and automation.

The next great CPU won't build itself. We’re assembling a world-class team across every layer of CPU development, from architecture and design to verification, physical implementation, software, infrastructure, and product delivery. Every discipline matters, and every person has the opportunity to help shape the technology from the ground up.